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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling Softcover reprint of the original 1st ed. 2014 Edition
Author(s): Ayan Mandal (Author), Sunil P. Khatri (Author), Rabi Mahapatra (Author)
- Publisher: Springer
- Publication Date: 23 Aug. 2016
- Edition: Softcover reprint of the original 1st ed. 2014
- Language: English
- Print length: 156 pages
- ISBN-10: 1493948172
- ISBN-13: 9781493948178
Book Description
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
Editorial Reviews
From the Back Cover
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
