Reconfigurable Networks-on-Chip 2012th Edition

From the reviews:

“This monograph reviews the fundamental theories, architectures, algorithms, and state-of-the-art development of NoC. The book begins with an overview of the communication-centric design for multi-processor system-on-chip (MP-SoC) and conventional NoC architectures, followed by an extended introduction to the design methodology of NoC. The book concludes with a case study of bidirectional NoC (BiNoC) architecture. … Overall, this monograph provides an in-depth, academic introduction to the design methodology of NoC architecture. … It is suitable for academic researchers and professionals working with NoC.” (Jun Liu, ACM Computing Reviews, July, 2012)

This book provides a comprehensive survey of recent progress in the design and implementation of Networks-on-Chip. It addresses a wide spectrum of on-chip communication problems, ranging from physical, network, to application layers. Specific topics that are explored in detail include packet routing, resource arbitration, error control/correction, application mapping, and communication scheduling. Additionally, a novel bi-directional communication channel NoC (BiNoC) architecture is described, with detailed explanation.

• Written for practicing engineers in need of practical knowledge about the design and implementation of networks-on-chip;
• Includes tutorial-like details to introduce readers to a diverse range of NoC designs, as well as in-depth analysis for designers with NoC experience to explore advanced issues;
• Describes a variety of on-chip communication architectures, including a novel bi-directional communication channel NoC.

From the Foreword:

Overall this book shows important advances over the state of the art that will affect future system design as well as R&D in tools and methods for NoC design. It represents an important reference point for both designers and electronic design automation researchers and developers.

–Giovanni De Micheli